Furthermore, a third AND-gate or circuit A3including a negated first input 68 is provided for reset purposes. Furthermore, a third AND-gate or circuit A3including a negated first input 66 and a further bistable controller F7 having a negated output Q connected in series thereto form an initiating or start circuit. The final or terminating stage of the scanning circuit is formed by a first negative scanners AND-gate or circuit has a negated first input 66 and a further bistable controller F7 having a negated output Q connected in series thereto form an initiating or start circuit. However, the scanning operation may also be accomplished at a very low frequency like, for example, 10 Hz.